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W631GG6KB
8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap (see Figure 86). In
this case, the response of the DDR3 SDRAMs R TT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD
entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case the response of the DDR3 SDRAMs R TT
to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD exit transition period to the end of the PD entry
transition period. Note that in the bottom part of Figure 86 it is assumed that there was no Refresh command in progress when Idle state was entered.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
Command
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
t ANPD
t RFC (min)
PD entry transition period
PD exit transition period
CKE
t ANPD
t ANPD
short CKE low transition period
short CKE high transition period
t XPDLL
t XPDLL
TIME BREAK
TRANSITIONING
DON'T CARE
Figure 86 – Transition period for short CKE cycles, entry and exit period overlapping (AL = 0, WL = 5, t ANPD = WL - 1 = 4)
Publication Release Date: Dec. 09, 2013
Revision A05
- 93 -
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